The present invention is directed to a surface mount semiconductor device and to a method of assembling a surface mount semiconductor device.
Semiconductor device packaging fulfills basic functions such as providing electrical connections and protecting the die against mechanical and environmental stresses. Continued progress in reduction of the size of the semiconductor dies and increased functionality and complexity of the circuits integrated in the dies require size reduction of the packaging with the same or greater complexity of the electrical connections with external circuits.
Semiconductor devices are commonly packaged for surface mounting by encapsulating one or more semiconductor dies with a mold compound. Electrical contacts for connection with external circuits are exposed in an active face of the package and are connected internally with electrical contact pads on the semiconductor die. Various techniques are available for connecting the exposed electrical contacts of the package internally with the embedded semiconductor die.
In a wire bonded package, the semiconductor die may be mounted on a substrate with the bond pads of the semiconductor die on the active face of the die opposite from the substrate. Wires are then bonded to the die bond pads and to the exposed electrical contacts of the package to provide the internal connections. The substrate may be an electrically conductive lead frame, whose frame members are cut off and discarded during production after applying molding compound to encapsulate the semiconductor die, the internal connections and the exposed electrical contacts from the lead frame. This technique is limited to devices where the exposed electrical contacts of the package are disposed around the periphery of the semiconductor die.
In an example of a flip-chip technique, the contact pads of the semiconductor die (or ‘chip’) on its active face are metallized and solder balls or studs are applied to the contact pads, typically before singulation of the dies from the wafer. The singulated dies are then placed with their active face on external circuits or on a printed circuit board substrate bearing an array of corresponding external contacts. The solder is then re-melted, typically using an ultrasonic or alternatively a reflow solder process to establish the electrical connections. This technique requires the same identical geometry for the array of external contacts as for the array of contact pads on the semiconductor die. Accordingly, the distribution of connections between the external contacts and the semiconductor die is imposed and any redistribution has to be provided by the external circuits. If the package contains more than one die, any interconnection between the dies has to be provided by the external circuits. Moreover, a minimum spacing of the solder balls or studs is required to avoid risk of short circuits.
In a technique known as ‘redistributed chip packaging’, singulated dies are placed temporarily with their active face on a substrate. The dies are embedded with a molding compound into a panel and then released from the substrate. The pads on the die surfaces are then connected to exposed pads on the surface of the package panel by a redistribution process to route out the signal connections, and the power and ground connections. The redistribution process comprises deposition of a plurality of electrically conductive layers by electroplating techniques, separated by insulating layers and patterned using batch process lithography. However, the process requires deposition and patterning of several layers, requiring precision aligning and several extra process steps, especially for complex redistribution.